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5 v, slew-rate limited, half-duplex and full-duplex rs-485/rs-422 transceivers adm4850/adm4851/adm4852/adm4853/ adm4854/adm4855/adm4856/adm4857 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2012 analog devices, inc. all rights reserved. features eia rs-485-/rs-422-compliant data rate options adm4850/adm4854: 115 kbps adm4851/adm4855: 500 kbps adm4852/adm4856: 2.5 mbps adm4853/adm4857: 10 mbps half- and full-duplex options reduced slew rates for low emi true fail-safe receiver inputs 5 a (maximum) supply current in shutdown mode up to 256 transceivers on one bus outputs high-z when disabled or powered off ?7 v to +12 v bus common-mode range thermal shutdown and short-circuit protection pin-compatible with the max308x specified over the ?40c to +85c temperature range available in 8-lead soic, lfcsp, and msop packages qualified for automotive applications applications low power rs-485 applications emi-sensitive systems dte-dce interfaces industrial control packet switching local area networks level translators functional block diagrams 04931-001 ro re r de di d a b gnd v cc adm4850/adm4851/ adm4852/adm4853 figure 1. 04931-028 ro r a b di d z y gnd v cc adm4854/adm4855/ adm4856/adm4857 figure 2. general description the adm4850/adm4851/adm4852/adm4853/adm4854/ adm4855/adm4856/adm4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. they are designed for balanced data transmission and comply with eia standards rs-485 and rs-422. the adm4850/adm4851/adm4852/adm4853 are half- duplex transceivers that share differential lines and have separate enable inputs for the driver and receiver. the full-duplex adm4854/adm4855/adm4856/adm4857 transceivers have dedicated differential line driver outputs and receiver inputs. the parts have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. because only one driver should be enabled at any time, the output of a disabled or pow- ered-down driver is three-stated to avoid overloading the bus. the receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. this guarantees that the receiver outputs are in a known state before communication begins and when communication ends. the driver outputs are slew-rate limited to reduce emi and data errors caused by reflections from improperly terminated buses. excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. the parts are fully specified over the commercial and industrial temperature ranges and are available in 8-lead soic, lfcsp (adm4850/adm4851/adm4852/adm4853), and msop (adm4850 only) packages. table 1. selection table part no. half-/full-duplex data rate adm4850 half 115 kbps adm4851 half 500 kbps adm4852 half 2.5 mbps adm4853 half 10 mbps adm4854 full 115 kbps adm4855 full 500 kbps adm4856 full 2.5 mbps adm4857 full 10 mbps
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 adm4850/adm4854 timing specifications........................... 4 adm4851/adm4855 timing specifications........................... 4 adm4852/adm4856 timing specifications........................... 5 adm4853/adm4857 timing specifications........................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 test circuits..................................................................................... 11 switching characteristics .............................................................. 12 circuit description......................................................................... 13 slew-rate control ...................................................................... 13 receiver input filtering............................................................. 13 half-/full-duplex operation ................................................... 13 high receiver input impedance .............................................. 14 three-state bus connection..................................................... 14 shutdown mode ......................................................................... 14 fail-safe operation .................................................................... 14 current limit and thermal shutdown ................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 automotive product................................................................... 16 revision history 1/12rev. c to rev. d change to features section ............................................................. 1 changes to ordering guide .......................................................... 15 added automotive products section .......................................... 15 1/11rev. b to rev. c change to table 8, pin 3 description ............................................ 7 changes to figure 29...................................................................... 12 changes to ordering guide .......................................................... 15 7/09rev. a to rev. b added msop package .................................................. throughout changes to table 2............................................................................ 3 changes to table 7............................................................................ 6 added figure 4; renumbered figures sequentially..................... 7 moved typical performance characteristics section .................. 8 changes to figure 24, figure 27 ................................................... 11 changes to figure 29...................................................................... 12 change to shutdown mode section............................................. 13 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 4/09rev. 0 to rev. a changes to ordering guide .......................................................... 15 10/04revision 0: initial version
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 3 of 16 specifications v cc = 5 v 5%, t a = t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments driver differential output voltage, v od v cc v r = , see figure 18 1 2.0 5 v r = 50 (rs-422), see figure 18 1.5 5 v r = 27 (rs-485), see figure 18 |v od3 | 1.5 5 v v tst = ?7 v to 12 v, see figure 19 ?|v od | for complementary output states 0.2 v r = 27 or 50 , see figure 18 common-mode output voltage, v oc 3 v r = 27 or 50 , see figure 18 ?|v oc | for complementary output states 0.2 v r = 27 or 50 , see figure 18 output short-circuit current, v out = high ?200 +200 ma ?7 v < v out < +12 v output short-circuit current, v out = low ?200 +200 ma ?7 v < v out < +12 v driver input logic cmos input logic threshold low 0.8 v cmos input logic threshold high 2.0 v cmos logic input current (di) 1 a de input resistance to gnd 220 k receiver differential input threshold voltage, v th ?200 ?125 ?30 mv ?7 v < v oc < +12 v input hysteresis 20 mv ?7 v < v oc < +12 v input resistance (a, b) 96 150 k ?7 v < v oc < +12 v input current (a, b) 0.125 ma v in = +12 v ? 0 . 1 m a v in = ?7 v cmos logic input current ( re ) 1 a cmos output voltage low 0.4 v i out = +4 ma cmos output voltage high 4.0 v i out = ?4 ma output short-circuit current 7 85 ma v out = gnd or v cc three-state output leakage current 2 a 0.4 v v out 2.4 v power supply current 115 kbps options (adm4850/adm4854) 5 a de = 0 v, re = v cc (shutdown) 36 60 a de = 0 v, re = 0 v 100 160 a de = v cc 500 kbps options (adm4851/adm4855) 5 a de = 0 v, re = v cc (shutdown) 80 120 a de = 0 v, re = 0 v 120 200 a de = v cc 2.5 mbps options (adm4852/adm4856) 5 a de = 0 v, re = v cc (shutdown) 250 400 a de = 0 v, re = 0 v 320 500 a de = v cc 10 mbps options (adm4853/adm4857) 5 a de = 0 v, re = v cc (shutdown) 250 400 a de = 0 v, re = 0 v 320 500 a de = v cc 1 guaranteed by design.
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 4 of 16 adm4850/adm4854 timing specifications v cc = 5 v 5%, t a = t min to t max , unless otherwise noted. table 3. parameter min typ max unit test conditions/comments driver maximum data rate 115 kbps propagation delay, t plh , t phl 600 2500 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 skew, t skew 70 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 rise/fall times, t r , t f 600 2400 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 enable time, t zh 2000 ns r l = 500 , c l = 100 pf, see figure 21 , adm4850 disable time, t zl 2000 ns r l = 500 , c l = 15 pf, see figure 21 , adm4850 enable time from shutdown 4000 ns r l = 500 , c l = 100 pf, see figure 21 , adm4850 receiver propagation delay, t plh , t phl 400 1000 ns c l = 15 pf, see figure 22 differential skew, t skew 255 ns c l = 15 pf, see figure 22 enable time 5 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4850 disable time 20 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4850 enable time from shutdown 4000 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4850 time to shutdown 50 330 3000 ns adm4850 1 1 the half-duplex device is put into shutdown mode by driving re high and de low. if these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. if the enable inputs are in this state for at least 3000 ns, the de vice is guaranteed to enter shutdown mo de. adm4851/adm4855 timing specifications v cc = 5 v 5%, t a = t min to t max , unless otherwise noted. table 4. parameter min typ max unit test conditions/comments driver maximum data rate 500 kbps propagation delay, t plh , t phl 250 600 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 skew, t skew 40 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 rise/fall times, t r , t f 200 600 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 enable time, t zh 1000 ns r l = 500 , c l = 100 pf, see figure 21 , adm4851 disable time, t zl 1000 ns r l = 500 , c l = 15 pf, see figure 21 , adm4851 enable time from shutdown 4000 ns r l = 500 , c l = 100 pf, see figure 21 , adm4851 receiver propagation delay, t plh , t phl 400 1000 ns c l = 15 pf, see figure 22 differential skew, t skew 250 ns c l = 15 pf, see figure 22 enable time 5 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4851 disable time 20 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4851 enable time from shutdown 4000 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4851 time to shutdown 50 330 3000 ns adm4851 1 1 the half-duplex device is put into shutdown mode by driving re high and de low. if these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. if the enable inputs are in this state for at least 3000 ns, the de vice is guaranteed to enter shutdown mo de.
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 5 of 16 adm4852/adm4856 timing specifications v cc = 5 v 5%, t a = t min to t max , unless otherwise noted. table 5. parameter min typ max unit test conditions/comments driver maximum data rate 2.5 mbps propagation delay, t plh , t phl 50 180 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 skew, t skew 50 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 rise/fall times, t r , t f 140 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 enable time, t zh 180 ns r l = 500 , c l = 100 pf, see figure 21 , adm4852 disable time, t zl 180 ns r l = 500 , c l = 15 pf, see figure 21 , adm4852 enable time from shutdown 4000 ns r l = 500 , c l = 100 pf, see figure 21 , adm4852 receiver propagation delay, t plh , t phl 55 190 ns c l = 15 pf, see figure 22 differential skew, t skew 50 ns c l = 15 pf, see figure 22 enable time 5 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4852 disable time 20 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4852 enable time from shutdown 4000 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4852 time to shutdown 50 330 3000 ns adm4852 1 1 the half-duplex device is put into shutdown mode by driving re high and de low. if these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. if the enable inputs are in this state for at least 3000 ns, the de vice is guaranteed to enter shutdown mo de. adm4853/adm4857 timing specifications v cc = 5 v 5%, t a = t min to t max , unless otherwise noted. table 6. parameter min typ max unit test conditions/comments driver maximum data rate 10 mbps propagation delay, t plh , t phl 0 30 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 skew, t skew 10 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 rise/fall times, t r , t f 30 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 20 enable time, t zh 35 ns r l = 500 , c l = 100 pf, see figure 21 , adm4853 disable time, t zl 35 ns r l = 500 , c l = 15 pf, see figure 21 , adm4853 enable time from shutdown 4000 ns r l = 500 , c l = 100 pf, see figure 21 , adm4853 receiver propagation delay, t plh , t phl 55 190 ns c l = 15 pf, see figure 22 differential skew, t skew 30 ns c l = 15 pf, see figure 22 enable time 5 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4853 disable time 20 50 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4853 enable time from shutdown 4000 ns r l = 1 k, c l = 15 pf, see figure 23 , adm4853 time to shutdown 50 330 3000 ns adm4853 1 1 the half-duplex device is put into shutdown mode by driving re high and de low. if these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. if the enable inputs are in this state for at least 3000 ns, the de vice is guaranteed to enter shutdown mo de.
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 6 of 16 absolute maximum ratings table 7. parameter rating v cc to gnd 6 v digital i/o voltage (de, re , di, ro) ?0.3 v to v cc + 0.3 v driver output/receiver input voltage ?9 v to +14 v operating temperature range ?40c to +85c storage temperature range ?65c to +125c ja thermal impedance soic 110c/w lfcsp 62c/w msop 133.1c/w lead temperature soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 7 of 16 pin configurations and function descriptions ro 1 v cc 8 di 4 gnd 5 adm4850/ adm4851/ adm4852/ adm4853 top view (not to scale) re 2 b 7 04931-002 de a 6 3 pin 1 indicator notes 1. the exposed paddle on the underside of the package should be soldered to the ground plane to increase the reliability of the solder joints and to maximize the thermal capability of the package. 1 ro 2 re 3 de 4 di 7b 8v cc top view (not to scale) a dm4850/adm4851/ adm4852/adm4853 6a 5gnd 04931-029 figure 3. adm4850/adm4851/adm4852/adm4853 pin configuration, soic and msop figure 4. adm4850/adm4851/adm4852/adm4853 pin configuration, lfcsp table 8. adm4850/adm4851/adm4852/adm4853 pin descriptions pin no. mnemonic description 1 ro receiver output. when ro is enabled, if (a ? b) ?30 mv, ro = high; if (a ? b) ?200 mv, ro = low. 2 re receiver output enable. a low level on this pin enab les the receiver output, ro. a high level places ro into a high impedance state. 3 de driver output enable. a high level on this pin enables the driver differential outputs, a and b. a low level places them into a high impedance state. 4 di driver input. when the driver is enabled, a logic low on di forces a low and b high, whereas a logic high on di forces a high and b low. 5 gnd ground. 6 a noninverting receiver input a/noninverting driver output a. 7 b inverting receiver input b/inverting driver output b. 8 v cc 5 v power supply.
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 8 of 16 v cc 1 a 8 gnd 4 y 5 adm4854/ adm4855/ adm4856/ adm4857 top view (not to scale) ro 2 b 7 04931-003 di z 6 3 figure 5. adm4854/adm4855/adm4856/adm4857 pin configuration, soic table 9. adm4854/adm4855/adm4856/adm4857 pin descriptions pin no. mnemonic description 1 v cc 5 v power supply. 2 ro receiver output. when ro is enabled, if (a ? b) ?30 mv, ro = high; if (a ? b) ?200 mv, ro = low. 3 di driver input. when the driver is enabled, a logic low on di forces y low and z high, whereas a logic high on di forces y high and z low. 4 gnd ground. 5 y noninverting driver output. 6 z inverting driver output. 7 b inverting receiver input. 8 a noninverting receiver input.
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 9 of 16 typical performance characteristics 400 0 50 100 150 200 250 300 350 ?50 ?25 0 25 50 75 100 125 04931-014 temperature (c) unloaded supply current ( a) adm4853: de = v cc adm4853: de = gnd adm4850: de = v cc adm4850: de = gnd figure 6. unloaded supply current vs. temperature 04931-015 50 0 5 10 15 20 25 30 35 40 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 receiver output low voltage (v) receiver output current (ma) figure 7. receiver output current vs. receiver output low voltage 04931-016 5 0 ?5 ?10 ?15 ?20 3.5 4.0 4.5 5.0 5.5 receiver output high voltage (v) receiver output current (ma) figure 8. receiver output current vs. receiver output high voltage 04931-017 0.40 0.15 0.20 0.25 0.30 0.35 ?50?250 255075100125 temperature ( c) output low voltage (v) figure 9. receiver output low voltage vs. temperature 04931-018 4.6 4.0 4.1 4.2 4.3 4.4 4.5 ?50 ?25 0 25 50 75 100 125 temperature (c) output high voltage (v) figure 10. receiver output high voltage vs. temperature 04931-019 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 differential output voltage (v) driver output current (ma) figure 11. driver output current vs. differential output voltage
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 10 of 16 04931-020 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output voltage (v) output current (ma) figure 12. output current vs . driver output low voltage 04931-021 ?10 ?30 ?50 ?70 ?90 ?110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output voltage (v) output current (ma) figure 13. output current vs. driver output high voltage 450 0 50 100 150 200 250 300 350 400 ?50 ?25 0 25 50 75 100 125 04931-022 temperature (c) propagation delay (ns) adm4855 adm4853 figure 14. driver propagation delay vs. temperature 800 700 600 500 400 300 200 100 0 ?50 ?25 0 25 50 75 100 125 04931-023 temperature (c) propagation delay (ns) adm4855 adm4853 figure 15. receiver propagation delay vs. temperature 04931-024 ch1 1.00v ? b w ch2 1.00v ? b w m 400ns ch3 2.00v ch3 2.00v ? b w ch4 5.00v ? 3 2 4 figure 16. driver/receiver propagation delay (adm4855, 500 kbps) 04931-025 ch1 2.00v ? b w ch2 1.00v ? m 50.0ns ch1 480mv ch3 1.00v ? b w ch4 5.00v ? 1 2 4 figure 17. driver/receiver propagation delay (adm4857, 4 mbps)
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 11 of 16 test circuits 04931-004 v od r r v oc figure 18. driver voltage measurement 04931-005 v od3 60 ? 375? 375? v tst figure 19. driver voltage measurement over common-mode voltage range 04931-006 c l1 c l2 r ldiff a b figure 20. driver propagation delay 04931-007 r l v cc s2 v out de in 0v or 3v de s1 b a c l figure 21. driver enable/disable 04931-008 re b a c l v out figure 22. receiver propagation delay re 04931-009 r l v cc s2 v out s1 c l +1.5v ?1.5v re in figure 23. receiver enable/disable
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 12 of 16 switching characteristics 04931-010 3 v 0v 5v 0v a b v od t r t f t plh t phl 90% point 10% point 90% point 10% point t skew = |t plh ? t phl | 1/2v od 1.5v 1.5v figure 24. driver propagation delay, rise/fall timing 04931-011 t skew = |t plh ? t phl | 1.5v 1.5v t plh t phl ro v oh 0v a , b 0v v ol figure 25. receiver propagation delay 04931-012 a , b a , b de 3v 0v 0v v oh v ol 1.5v t lz t zl 1.5v t hz t zh 2.3v 2.3v v ol + 0.5v v oh ? 0.5v figure 26. driver enable/disable timing 04931-013 ro ro re 3v 0v 0v v oh v ol 1.5v t lz t zl 1.5v t hz t zh 1.5v 1.5v v ol + 0.5v v oh ? 0.5v output high output low figure 27. receiver enable/disable timing
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 13 of 16 circuit description the adm4850/adm4851/adm4852/adm4853/adm4854/ adm4855/adm4856/adm4857 are high speed rs-485/ rs-422 transceivers offering enhanced performance over industry-standard devices. all devices in the family contain one driver and one receiver, but offer a choice of performance options. the devices feature true fail-safe operation, which means that a logic high receiver output is guaranteed when the receiver inputs are open-circuit or short-circuit, or when they are connected to a terminated transmission line with all drivers disabled (see the fail-safe operation section). slew-rate control the adm4850 and adm4854 feature a controlled slew-rate driver that minimizes electromagnetic interference (emi) and reduces reflections caused by incorrectly terminated cables, allowing error-free data transmission rates up to 115 kbps. the adm4851 and adm4855 offer a higher limit on driver output slew rate, allowing data transmission rates up to 500 kbps. the driver slew rates of the adm4852 and adm4856 and the adm4853 and adm4857 are not limited, offering data transmission rates up to 2.5 mbps and 10 mbps, respectively. receiver input filtering the receivers of all the devices incorporate input hysteresis. in addition, the receivers of the 115 kbps adm4850 and adm4854 and the 500 kbps adm4851 and adm4855 incorporate input filtering. this enhances noise immunity with differential signals that have very slow rise and fall times. however, it causes the propagation delay to increase by 20%. half-/full-duplex operation half-duplex operation implies that the transceiver can transmit and receive, but it can do only one of these at any given time. how- ever, with full-duplex operation, the transceiver can transmit and receive simultaneously. the adm4850/adm4851/adm4852/ adm4853 are half-duplex devices in which the driver and the receiver share differential bus terminals. the adm4854/ adm4855/adm4856/adm4857 are full-duplex devices that have dedicated driver output and receiver input pins. figure 28 and figure 29 show typical half- and full-duplex topologies. 04931-026 ro re de di d r a b maximum number of transceivers on bus: 256 ro re de di d r a b r d ro re de di ab r d ro re de di ab adm4850/adm4851/ adm4852/adm4853 adm4850/adm4851/ adm4852/adm4853 adm4850/adm4851/ adm4852/adm4853 adm4850/adm4851/ adm4852/adm4853 figure 28. typical half-duplex rs-485 network topology 04931-027 gnd ro di d r a b ro di d a b z y r gnd v cc v cc z y adm4854/adm4855/ adm4856/adm4857 adm4854/adm4855/ adm4856/adm4857 figure 29. typical full-duplex point-to-point rs-485 network topology
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 14 of 16 high receiver input impedance the input impedance of the adm4850/adm4851/adm4852/ adm4853/adm4854/adm4855/adm4856/adm4857 receivers is 96 k, which is eight times higher than the standard rs-485 unit load of 12 k. this 96 k impedance enables a standard driver to drive 32 unit loads or to be connected to 256 adm4850/ adm4851/adm4852/adm4853/adm4854/adm4855/ adm4856/adm4857 receivers. an rs-485 bus, driven by a single standard driver, can be connected to a combination of adm4850/adm4851/adm4852/adm4853/adm4854/ adm4855/adm4856/adm4857 devices and standard unit load receivers, up to an equivalent of 32 standard unit loads. three-state bus connection the half-duplex parts (adm4850/adm4851/adm4852/ adm4853) have a driver enable (de) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. similarly, the half-duplex devices have an active low receiver enable ( re ) pin. taking this pin low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state. this allows several driver outputs to be connected to an rs-485 bus. note that only one driver should be enabled at a time, but that many receivers can be enabled. shutdown mode the adm4850/adm4851/adm4852/adm4853 have a low power shutdown mode, which is enabled by taking re high and de low. if shutdown mode is not used, the fact that de is active high and re is active low offers a convenient way of switching the device between transmit and receive by tying de and re together. if de is driven low and re is driven high for less than 50 ns, the devices are guaranteed not to enter shutdown mode. if de is driven low and re is driven high for at least 3000 ns, the devices are guaranteed to enter shutdown mode. fail-safe operation the adm4850/adm4851/adm4852/adm4853/adm4854/ adm4855/adm4856/adm4857 offer true fail-safe operation while remaining fully compliant with the 200 mv eia/tia-485 standard. a logic high receiver output is generated when the receiver inputs are shorted together or open circuit, or when they are connected to a terminated transmission line with all drivers disabled. this is done by setting the receiver threshold between ?30 mv and ?200 mv. if the differential receiver input voltage (a ? b) is greater than or equal to ?30 mv, ro is logic high. if (a ? b) is less than or equal to ?200 mv, ro is logic low. in the case of a terminated bus with all transmitters disabled, the differential input voltage of the receiver is pulled to 0 v by the internal circuitry of the adm4850/adm4851/adm4852/ adm4853/adm4854/adm4855/adm4856/adm4857, which results in a logic high with 30 mv minimum noise margin. current limit and thermal shutdown the adm4850/adm4851/adm4852/adm4853/adm4854/ adm4855/adm4856/adm4857 incorporate two protection mechanisms to guard the drivers against short circuits, bus con- tention, or other fault conditions. the first is a current limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 ma. under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150c, and does not turn them back on until the temperature falls to 130c.
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 15 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 30. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 31. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeter s 0 90308-b 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 32. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters
adm4850/adm4851/adm4852/adm4853/adm4854/adm4855/adm4856/adm4857 rev. d | page 16 of 16 ordering guide model 1 , 2 temperature range package description package option branding adm4850acpz-reel7 ?40c to +85c 8-lead lfcsp_vd cp-8-2 m8q adm4850arz ?40c to +85c 8-lead soic_n r-8 adm4850arz-reel7 ?40c to +85c 8-lead soic_n r-8 adm4850armz ?40c to +85c 8-lead msop rm-8 m8q adm4850armz-reel7 ?40c to +85c 8-lead msop rm-8 m8q adm4851arz ?40c to +85c 8-lead soic_n r-8 ADM4851ARZ-REEL7 ?40c to +85c 8-lead soic_n r-8 adm4852acpz-reel7 ?40c to +85c 8-lead lfcsp_vd cp-8-2 m9m adm4852arz ?40c to +85c 8-lead soic_n r-8 adm4852arz-reel7 ?40c to +85c 8-lead soic_n r-8 adm4853acpz-reel7 ?40c to +85c 8-lead lfcsp_vd cp-8-2 f0b adm4853arz ?40c to +85c 8-lead soic_n r-8 adm4853arz-reel7 ?40c to +85c 8-lead soic_n r-8 adm4853warz-rl7 ?40c to +85c 8-lead soic_n r-8 adm4854arz ?40c to +85c 8-lead soic_n r-8 adm4855ar-reel7 ?40c to +85c 8-lead soic_n r-8 adm4855arz ?40c to +85c 8-lead soic_n r-8 adm4856arz ?40c to +85c 8-lead soic_n r-8 adm4856arz-reel7 ?40c to +85c 8-lead soic_n r-8 adm4857arz ?40c to +85c 8-lead soic_n r-8 adm4857arz-reel7 ?40c to +85c 8-lead soic_n r-8 1 z = rohs compliant part. 2 w = qualified for automotive products. automotive product the adm 4853warz-rl7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; ther efore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are a vailable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for this model. ?2004C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04931-0-1/12(d)

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